1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a sidewall spacer having a generally triangular shape and to various semiconductor devices having such a sidewall spacer.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, whether an NFET or a PFET device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, a gate insulation layer and a gate electrode positioned above the gate insulation layer over the channel region. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. The rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconducting substrate by performing advanced implantation techniques through a masking layer. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.
An illustrative ion implantation sequence for forming source/drain regions for an illustrative prior art transistor 100 will now be discussed with reference to FIGS. 1A-1G. FIG. 1A depicts the transistor 100 at an early stage of fabrication, wherein a gate structure 14 has been formed above a silicon-on-insulator (SOI) substrate 10 that is comprised of a bulk substrate 10A, a buried insulation layer 10B (a so-called BOX layer) and an active layer 10C where semiconductor devices will be formed. An active region 13 is defined in the active layer 10C by a shallow trench isolation structure 11. The gate structure 14 typically includes a gate insulation layer 14A and a conductive gate electrode 14B. A gate cap layer 15, e.g., a layer of silicon nitride, is typically formed above the gate electrode 14B. The gate structure 14 and the gate cap layer 15 may be formed by forming layers of material that correspond to the gate insulation layer 14A, the gate electrode 14B and the gate cap layer 15 and thereafter patterning those layers of material using known etching and photolithography techniques. A first sidewall spacer 16A is formed adjacent the gate structure 14. The first sidewall spacer 16A is typically formed by conformably depositing a layer of spacer material and thereafter performing an anisotropic etching process. The first sidewall spacer 16A is sometimes referred to in the industry as “spacer zero,” and it may have a base thickness that falls within the range of about 8-15 nm, depending upon the particular application.
The masking layers that would be used during the implantation sequence shown in FIGS. 1A-1G are not depicted in the drawings. As shown in FIG. 1B, an initial ion implantation process 20 is typically performed to form so-called extension implant regions 20A in the substrate 10. Typically, the extension implant regions 20A will be self-aligned with respect to the first sidewall spacers 16A. In some applications, the first sidewall spacer 16A may be omitted. In such a case, the extension implant region 20A would be self-aligned relative to the sidewall of the gate structure 14. Then, as shown in FIG. 1C, a liner layer 17, e.g., silicon dioxide, and a second sidewall spacer 16B are formed proximate the gate structure 14. The liner layer 17 and the second sidewall spacer 16B are typically formed by conformably depositing a layer of the appropriate material. In the case of the spacer 16B, the spacer 16B is formed by performing an anisotropic etching process on the deposited layer of spacer material. Then, as shown in FIG. 1D, a second ion implantation process 22 is performed on the transistor 100 to form so-called deep source/drain implant regions 22A in the substrate 10. The ion implantation process 22 performed to form the deep source/drain implant regions 22A is typically performed using a higher dopant dose and a higher implant energy than the ion implantation process 20 that is performed to form the extension implant regions 20A.
Thereafter, as shown in FIG. 1E, a heating or anneal process is performed to form the final source/drain regions 24 for the transistor 100. This heating process repairs the damage to the lattice structure of the substrate material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice. During the anneal process, the implanted dopants migrate and the dope regions 20A, 22A (FIG. 1D) tend to merge together to a certain degree. Of course, the type of dopants implanted, either N-type or P-type dopants, depends upon the type of transistor being made, i.e., an NFET transistor or a PFET transistor, respectively. Such implantation processes are performed using well-known ion implantation systems.
FIG. 1F is an image of a transistor device taken with a scanning electron microscope. The various structures in the transistor that correspond to the gate insulation layer 14A, the gate electrode 14B, the first sidewall spacer 16A, the liner layer 17 and the second sidewall spacer 16B are identified by the same reference number. As depicted by the dashed line 25, the second sidewall spacer 16B has a cross-sectional configuration that has a general quadrilateral configuration with an upper surface and corner regions 25A that tends to be rounded to a certain degree.
FIG. 1G is an enlarged view of a portion of the device 100, taken where indicated in FIG. 1E. Fundamentally, during the source/drain implant process 22, the second sidewall spacer 16B acts as an implant mask with respect to the region 30 of the substrate that is under the spacer 16B. As a result, there tends to be less dopant material in the region 30, which means there is a higher resistance in this portion of the final source/drain region of the device 100 than is otherwise desirable. Such increased resistance leads to problems such as, for example, slower device operation, increased heating of the device, etc. Prior art efforts to reduce the impact of implanting through a sidewall spacer, such as the spacer 16B depicted in FIG. 1G, have involved forming one or more “L-shaped” spacers with the intent of producing an appropriately “graded” source/drain profile by partially implanting ions through the lateral “leg” of the L-shaped spacer. One drawback to this approach is that there is a limit on the amount of energy that can be used in the implant process through the L-shaped spacer. Moreover, due to the configuration of the L-shaped spacers, the implanted dopant materials tended to have a stepped-type configuration, and not the relatively smooth dopant gradient profile that is desirable for modern transistor devices.
The present disclosure is directed various methods of forming a sidewall spacer having a generally triangular shape for various semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.